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參數(shù)資料
| 型號(hào)： | MB91605PMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 80 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 58/68頁 |
| 文件大?。?/td> | 1435K |
| 代理商： | MB91605PMC |
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MB91605 Series
61
When operating in slave mode
(VDDE
= AVcc = 3.0 V to 3.6 V, VDDI = 1.65 V to 1.95 V, Vss = AVss = 0 V, Ta = 10 °C to + 70 °C)
*1 : tCYCP is peripheral clock cycle time.
*2 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system. In this case, the device
must satisfy the requirement of “tSUDAT
≥ 250 ns”.
When a device does not extend the “L” period of the SCL signal, the next data must be output to the SDA line
within 1250 ns (maximum SDA/SCL rise time + tSUDAT) from when the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to 6 MHz or higher.
*4 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.
Parameter
Sym-
bol
Pin
name
Condition
Typical mode
High-speed
mode*3
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
SDA0
to
SDA11,
SCL0
to
SCL11
R
= 1 k,
C
= 50 pF*4
01000400
kHz
“L” period of
SCL clock
tLOW
4.7
1.3
s
“H” period of
SCL clock
tHIGH
4.0
0.6
s
SCL
↓ → SDA
output delay time
tDLDAT
5 tCYCP*1
5 tCYCP*1
ns
Bus free time between
“STOP condition” and
“START condition”
tBUS
4.7
1.3
s
SDA data input
hold time
(vs. SCL
↓)
tHDDAT
2 tCYCP*1
2 tCYCP*1
s
SDA data input
setup time
(vs. SCL
↑)
tSUDAT
250
100*2
ns
“Repeated START
condition” setup time
SCL
↑ → SDA ↓
tSUSTA
4.7
0.6
s
“Repeated START
condition” hold time
SDA
↓ → SCL ↓
tHDSTA
4.0
0.6
s
The first
clock pulse
is generated
after this.
“STOP condition” set-
up time SCL
↑ → SDA
↑
tSUSTO
4.0
0.6
s
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