參數(shù)資料
型號(hào)： MB91605PMC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, MROM, 80 MHz, RISC MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-176
文件頁(yè)數(shù)： 13/68頁(yè)
文件大?。?/td> 1435K
代理商： MB91605PMC
MB91605 Series
20
■ RESTRICTIONS
1) Notes on the PS register
Some instructions write to the PS register in advance before executing. When a debugger is being used, execution
may break within an interrupt handler routine, or the values of the flags within the PS register may be updated
due to exception processing. However, the microcontroller is designed to reprocess correctly after returning from
the EIT, and to execute before and after the EIT proceeds according to the specifications.
If any of the following situations occur in the instruction immediately before a DIV0U or DIV0S instruction,
the processing in (1) to (3) will be performed.
- A user interrupt or NMI is accepted
- Step execution is performed
- A break occurs due to a data event or by being selected from the emulator menu
(1) The D0 and D1 flags are updated in advance.
(2) The EIT handling routine (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U or DIV0S instruction is executed and the D0/D1 flags are
updated back to the same value as in step (1).
If any of the OR CCR, ST ILM, or MOV Ri, PS instructions are executed to enable a user interrupt or NMI
interrupt source when that interrupt has occurred, the following operation will be performed.
(1) The PS register is updated in advance.
(2) The EIT handling routine (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS registers are updated
back to the same value as in step (1).
2) Watchdog timer
The watchdog timer is a function that monitors the program to check that it delays a reset within a certain
period of time, and resets the CPU if the program runs out of control and fails to delay the reset. Once the
watchdog timer has been enabled, it keeps running until reset. As an exception, the reset is automatically
delayed in conditions where the execution of the CPU program stops. It is possible that the watchdog timer
will not be triggered if these conditions arise as a result of the system running out of control. In that case,
please reset (INIT) using the external INIT pin.
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