參數(shù)資料
型號(hào)： MB91151APMC-G
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-144
文件頁(yè)數(shù)： 74/96頁(yè)
文件大?。?/td> 2300K
代理商： MB91151APMC-G
MB91151A Series
76
DS07-16312-2E
4.
AC Characteristics
(1) Clock Timing
(VCC
= 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
*1 : The target analog section is the A/D.
*2 : The maximum external bus operating frequency allowed is 25 MHz.
*3 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit
and the 1/8 gear are in use.
Parameter
Sym-
bol
Pin
name
Condition
Value
Unit
Remarks
Min
Max
Clock frequency
(high speed and self oscilla-
tion)
fC
X0, X1
10
18
MHz
Range in which self
oscillation is allowed
Clock frequency
(high speed and PLL in use)
Range in which self
oscillation and the
use of the PLL for ex-
ternal clock input are
allowed
Clock frequency
(High speed an 1/2 division
input)
10
18
MHz
Range in which exter-
nal clocks can be in-
put
Clock cycle time
tC
X0, X1
55.6
100
ns
Input clock pulse width
PWH
X0, X1
25
ns
PWL
15
ns
Input clock rising
tcr
X0, X1
8ns
(tcr
+tcf)
Input clock falling
tcf
Internal operat-
ing clock fre-
quency
CPU
system
fCP
One wait is
set with the
wait con-
troller.
0.625*3
36
MHz
Bus
system
fCPB
0.625*3
25*2
Peripheral
system
fCPP
0.625*3
33
Analog section ex-
cluded. *1
1
33
Analog section *1
Internal operat-
ing clock cycle
time
CPU
system
tCP
27.8
1600*3
ns
Bus
system
tCPB
40*2
1600*3
Peripheral
system
tCPP
30.3
1600*3
Analog section ex-
cluded. *1
30.3
1000
Analog section *1
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