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參數(shù)資料
| 型號： | MB91110PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 89/94頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | MB91110PMT2 |
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93
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
Figure 13-1. 16-bit Timer/Counter Block Diagram(1)
Note:
1.
Refer to
Table on page 5 for Timer/Counter 1 pin placement and description.
13.1.1 Registers
The Timer/Counter (TCNTn), output compare registers (OCRnx), and input capture register (ICRn) are all 16-bit registers.
Special procedures must be followed when accessing the 16-bit registers. These procedures are described in Section 13.2
“Accessing 16-bit Registers” on page 94. The Timer/Counter control registers (TCCRnx) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the timer interrupt flag
register (TIFRn). All interrupts are individually masked with the timer interrupt mask register (TIMSKn). TIFRn and TIMSKn are
not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The clock select
logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clkTn).
The double buffered output compare registers (OCRnx) are compared with the Timer/Counter value at all time. The result of the
compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pin
(OCnx). See Section 13.6 “Output Compare Units” on page 99 The compare match event will also set the compare match flag
(OCFnx) which can be used to generate an output compare interrupt request.
Control Logic
TCNTn
Timer/Counter
Count
Clear
Direction
clkTn
OCRnA
OCRnB
ICRn
TCCRnA
TCCRnB
=
Edge
Detector
(from Prescaler)
Clock Select
TOP
AC1ICE
ICPSEL1
RTG
BOTTOM
TOVn (Int. Req.)
OCnA (Int. Req.)
Tn
Waveform
Generation
Fixed
TOP
Value
DA
T
A
BUS
=
= 0
OCnA
OCnB (Int. Req.)
Waveform
Generation
Noise
Canceler
OCnB
Analog Comparator 1
Interrupt
ICFn (Int. Req.)
Edge
Detector
ICPnB
ICPnA
0
1
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