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參數(shù)資料
| 型號： | MB91110PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 81/94頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | MB91110PMT2 |
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86
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
Figure 12-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where
OCR0A is TOP.
Figure 12-10.Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O/8)
Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP.
Figure 12-11.Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
12.8
8-bit Timer/Counter Register Description
12.8.1 Timer/Counter Control Register A – TCCR0A
Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit
corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 12-2 on
page 87 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).
OCRnx - 1
clkI/O
(clkI/O/8)
TCNTn
OCRnx
OCFnx
clkTn
OCRnx
OCRnx + 1
OCRnx Value
OCRnx + 2
TOP - 1
clkI/O
(clkI/O/8)
TCNTn
(CTC)
OCRnx
OCFnx
clkTn
TOP
BOTTOM
TOP
BOTTOM + 1
Bit
7
6
5
4
3
2
1
0
COM0A1 COM0A0 COM0B1 COM0B0
–
WGM01
WGM00
TCCR0A
Read/Write
R/W
R
R/W
Initial Value
0
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相關(guān)代理商/技術(shù)參數(shù) |
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