參數(shù)資料
型號(hào)： MB91110PMT2
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁數(shù)： 86/94頁
文件大小： 1099K
代理商： MB91110PMT2
90
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
12.8.3 Timer/Counter Register – TCNT0
The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0)
while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0x registers.
12.8.4 Output Compare Register A – OCR0A
The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match
can be used to generate an output compare interrupt, or to generate a waveform output on the OC0A pin.
12.8.5 Output Compare Register B – OCR0B
The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match
can be used to generate an output compare interrupt, or to generate a waveform output on the OC0B pin.
12.8.6 Timer/Counter Interrupt Mask Register – TIMSK0
Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the status register is set, the Timer/Counter compare match B interrupt is
enabled. The corresponding interrupt is executed if a compare match in Timer/Counter occurs, i.e., when the OCF0B bit is set in
the Timer/Counter interrupt flag register – TIFR0.
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 compare match A interrupt
is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is
set in the Timer/Counter 0 interrupt flag register – TIFR0.
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 Overflow interrupt is enabled.
The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
Timer/Counter 0 interrupt flag register – TIFR0.
Bit
7654
3210
TCNT0[7:0]
TCNT0
Read/Write
R/W
Initial Value
0000
Bit
7654
3210
OCR0A[7:0]
OCR0A
Read/Write
R/W
Initial Value
0000
Bit
7654
321
0
OCR0B[7:0]
OCR0B
Read/Write
R/W
Initial Value
0000
000
0
Bit
765
4
3
2
1
0
–
OCIE0B
OCIE0A
TOIE0
TIMSK0
Read/Write
R
R/W
Initial Value
0
相關(guān)PDF資料
PDF描述
MB91110PMT2 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
MB91121PFV 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120
MB91154PFV-G-XXX 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP144
MB91F155APFV-G 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
MB91233LLGA-G-xxx-BNDE1 32-BIT, FLASH, 33.6 MHz, RISC MICROCONTROLLER, PQFP120
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB911110PMT2 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller
MB91121 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller
MB91121PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller CMOS
MB91133 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller
MB91133PBT 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*