參數(shù)資料
型號： MB90V650A
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數(shù)： 58/120頁
文件大小： 1690K
代理商： MB90V650A
58
MB90650A Series
(3) Input Capture
The input capture consists of two independent external input pins, their corresponding capture registers, and
a control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt
generated when the specified edge is detected on the signal from the external input pin.
The edge to detect on the external input signal is selectable.
Detection of rising edges, falling edges, or either edge can be specified.
The two input capture channels can operate independently.
An interrupt can be generated on detection of the specified edge on the external input signal.
The input capture interrupt can activate the intelligent I/O service.
Register details
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input
waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)
Block diagram
IPCP0 : 000060
H
IPCP1 : 000062
H
: Read only
: Indeterminate
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
R
R
R
X
R
R
R
R
R
Initial value
XXXXXXXX
B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IPCP0 : 000061
H
IPCP1 : 000063
H
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
R
R
R
R
R
R
R
Initial value
XXXXXXXX
B
Input capture register channel 0, channel 1 (IPCP0, IPCP1)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
000064
H
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000
B
Input capture control status register (ICS0, 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
: Readable and writable
Capture data register 0
Edge detection
Interrupt
16-bit timer/counter value (T15 to T00)
Interrupt
IN0
Capture data register 1
Edge detection
EG11 EG10 EG01 EG00
ICP1
ICP0
ICE1
ICE0
IN1
I
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