參數(shù)資料
型號(hào)： MB90P641APFV
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 17 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 67/94頁
文件大?。?/td> 1542K
代理商： MB90P641APFV
7
MB90640A Series
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
Pin no.
Pin name
Circuit
type
Function
LQFP*1
QFP*2
70
72
P50
I
(CMOS)
General purpose I/O port
This applies when CLK output is disabled.
CLK
CLK output pin
This applies when CLK output is enabled.
71
73
P51
K
(TTL)
General purpose I/O port
This applies when the external ready function is disabled.
RDY
Ready input pin
This applies when the external ready function is enabled.
72
74
P52
I
(CMOS)
General purpose I/O port
This applies when the hold function is disabled.
HAK
Hold acknowledge output pin
This applies when the hold function is enabled.
73
75
P53
K
(TTL)
General purpose I/O port
This applies when the hold function is disabled.
HRQ
Hold request input pin
This applies when the hold function is enabled.
74
76
P54
I
(CMOS)
General purpose I/O port
This applies in 8-bit external bus mode or when output is
disabled for the WRH pin.
WRH
Write strobe output pin for the upper 8 bits of the data bus
This applies in 16-bit external bus mode and when output is
enabled for the WRH pin.
76
78
P55
I
(CMOS)
General purpose I/O port
This applies when output is disabled for the WRL pin.
WRL
Write strobe output pin for the lower 8 bits of the data bus
This applies when output is enabled for the WRL pin.
77
79
P56
I
(CMOS)
General-purpose I/O port
This port is available in the single-chip mode.
RD
Read strobe output pin for the data bus
78
80
P57
I
(CMOS)
General-purpose I/O port
This port is available in the single-chip mode.
ALE
Address latch enable output pin
36 to 39,
41 to 44
38 to 41,
43 to 46
P60 to P67
C
Open-drain output ports
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