參數(shù)資料
型號： MB90P641APFV
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 17 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 36/94頁
文件大小： 1542K
代理商： MB90P641APFV
41
MB90640A Series
6. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two
request levels (“H” and “L”) are provided for extended intelligent I/O service. For external interrupt requests,
generation of interrupts on a rising or falling edge as well as on “H”, “L” levels can be selected, giving a total of
four types.
(1)
Register Configuration
(2)
Block Diagram
Address :
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Initial value
: 000028H
: 000029H
00000000B
Address :
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Initial value
XXXXXXXXB
: 00002BH
Address :
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Initial value
00000000B
: 00002AH
Address :
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Initial value
00000000B
R/W
X : Indeterminate
: Readable and writable
ELVR
EIRR
ENIR
Interrupt/DTP enable register
Interrupt/DTP source register
Request level setting register upper
Request level setting register lower
8
Interrupt/DTP enable register
Interrupt/DTP register
Request level setting register
Gate
Request F/F
Edge detect circuit
Request input
Interrupt input
Internal
data
bus
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