參數(shù)資料
型號(hào)： MB90P641APFV
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 17 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 31/94頁
文件大小： 1542K
代理商： MB90P641APFV
37
MB90640A Series
4. 16-bit Reload Timer (with Event Count Function)
The 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, input pin (TIN), output pin
(TOT), and a control register. The input clock can be selected from one external clock and three types of internal
clock. The output (TOT) outputs a toggle waveform in reload mode and a rectangular waveform during counting
in one-shot mode. The input (TIN) functions as the event input in event count mode and as the trigger input or
gate input in internal clock mode.
Input and output of timer pin TIM0 to TIM4 are set by way of the timer pin control register.
This product has five internal 16-bit reload timer channels.
(1)
Register Configuration
: 000039H
: 00003DH
: 000059H
: 00005DH
: 000061H
Address :
: 000038H
: 00003CH
: 000058H
: 00005CH
: 000060H
Address :
: 00003BH
: 00003FH
: 00005BH
: 00005FH
: 000063H
Address :
: 00003AH
: 00003EH
: 00005AH
: 00005EH
: 000062H
Address :
————
CSL1
CSL0 MOD2 MOD1
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
—
R/W
Initial value
---- 0000B
MOD0 OUTE OUTL RELD
INTE
UF
CNTE
TRG
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Initial value
00000000B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Initial value
XXXXXXXXB
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXXB
R/W
—
X
: Readable and writable
: Unused
: Indeterminate
TMR0/TMRLR0
TMR1/TMRLR1
TMR2/TMRLR2
TMR3/TMRLR3
TMR4/TMRLR4
TMR0/TMRLR0
TMR1/TMRLR1
TMR2/TMRLR2
TMR3/TMRLR3
TMR4/TMRLR4
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR4
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR4
Timer control status register upper
Timer control status register lower
16-bit timer register upper/16-bit reload register upper
16-bit timer register lower/16-bit reload register lower
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