參數(shù)資料
型號： MB90F949APF
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 7/57頁
文件大小： 1586K
代理商： MB90F949APF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7544 Group
MITSUBISHI MICROCOMPUTERS
15
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to change.
Fig. 15 Block diagram of ports (1)
(5)Port P11
Data bus
Port latch
Serial I/O output
P11/TxD P-channel output disable bit
(4)Port P10
(1)Port P00
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
CNTR1 interrupt input
(2)Ports P01, P02, P04–P07
(3)Port P03
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Timer output
P03/TXOUT
output valid
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Direction
register
Serial I/O enable bit
Transmit enable bit
(6)Port P12
Serial I/O clock output
Serial I/O mode selection bit
Serial I/O enable bit
Serial I/O synchronous
clock selection bit
Direction
register
Data bus
Port latch
Serial I/O clock input
P10, P12
input level
selection bit
*
Direction
register
Data bus
Port latch
Serial I/O enable bit
Receive enable bit
Serial I/O input
P10, P12
input level
selection bit
*
P10, P12, P34 and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
P00 key-on wakeup
selection bit
When the TTL level is selected, there is no hysteresis characteristics.
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