參數(shù)資料
型號： MB90F949APF
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 56/57頁
文件大?。?/td> 1586K
代理商： MB90F949APF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7544 Group
MITSUBISHI MICROCOMPUTERS
8
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Execute JSR
On-going Routine
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
Execute RTS
(PCL)
M (S)
(S)
(S – 1)
(S)
(S + 1)
(S)
(S + 1)
(PCH)
M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack
M (S)
(PS)
Execute RTI
(PS)
M (S)
(S)
(S – 1)
(S)
(S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
(PCL)
M (S)
(S)
(S + 1)
(S)
(S + 1)
(PCH)
M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 8 Register push and pop at interrupt generation and subroutine call
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