參數(shù)資料
型號： MB90F949APF
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 48/57頁
文件大?。?/td> 1586K
代理商： MB90F949APF
7544 Group
Rev.1.04
2004.06.08
page 62 of 66
REJ03B0012-0104Z
Notes on Timers
1. When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
2. When a count source of timer X is switched, stop a count of the
timer.
Notes on Timer 1
1. Timer 1 count source
The “on-chip oscillator output” of timer 1 count source selection
bits (bits 1 and 0 of timer count source set register 2 (address
2F16)) can be selected while the on-chip oscillator oscillation con-
trol bit (bit 3 of CPU mode register (address 3B16)) is “0” (on-chip
oscillator oscillation enabled).
Notes on Timer A
1. CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit (bit 6 of timer A mode register (address 1D16)).
When this bit is “0”, the CNTR1 interrupt request bit goes to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit goes to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
2. Period measurement mode, event counter mode and pulse
width HL continuously measurement mode
Set the direction register of port P00, which is also used as CNTR1
pin, to input.
Set the key-on wakeup function of P00, which is also used as
CNTR1 pin, to be disabled by setting the P00 key-on wakeup se-
lection bit (bit 7 of interrupt edge selection register (address 3A16))
to “1”.
3. Timer A count source
The “on-chip oscillator output” of timer A count source selection
bits (bits 3 and 2 of timer count source set register 2 (address
2F16)) can be selected while the on-chip oscillator oscillation con-
trol bit (bit 3 of CPU mode register (address 3B16)) is “0” (on-chip
oscillator oscillation enabled).
Notes on Timer X
1. CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit (bit 2 of timer X mode register (address 2B16)).
When this bit is “0”, the CNTR0 interrupt request bit goes to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit goes to “1” at the rising edge of
CNTR0 pin input signal.
2. Timer X count source selection
The f(XIN) (frequency not divided) can be selected by the timer X
count source selection bits (bits 1 and 0 of timer count source set
register 1 (address 2E16)) only when the ceramic oscillation or the
on-chip oscillator is selected.
Do not select it for the timer X count source at the RC oscillation.
3. Pulse output mode
Set the direction register of port P14, which is also used as CNTR0
pin, to output.
When the TXOUT pin is used, set the direction register of port P03,
which is also used as TXOUT pin, to output.
4. Pulse width measurement mode
Set the direction register of port P14, which is also used as CNTR0
pin, to input.
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