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參數(shù)資料
| 型號(hào)： | MB90F423GA |
| 廠商： | Fujitsu Limited |
| 英文描述： | Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125 |
| 中文描述： | 16位微控制器原件 |
| 文件頁(yè)數(shù)： | 42/99頁(yè) |
| 文件大?。?/td> | 1706K |
| 代理商： | MB90F423GA |
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MB90420G/5G (A) Series
42
6.
PPG Timer
The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting,
and 16-bit compare register with buffer for duty setting, plus pin control circuits.
The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output
pulse can be adjusted by rewriting the values in the two 16-bit registers.
(1) PWM function
Programmable to output a pulse, synchronized with a trigger.
Can also be used as a D/A converter with an external circuit.
(2) One-shot function
Detects the edge of a trigger input, and outputs a single pulse.
(3) Pin control
Set to “1” at a duty match (priority) .
Reset to “0” at a counter borrow event
Has a fixed output mode to output a simple all “L” ( or “H”) signal.
Polarity can be specified
(4) 16-bit down counter
Select from four types of counter operation clocks. Four internal clocks (
φ
,
φ
/4,
φ
/16,
φ
/64)
cycles.
The counter value can be initialized to “FFFF
H
” at a reset or counter borrow event.
φ
: Machine clock
(5) Interrupt requests
Timer startup
Counter borrow event (period match)
Duty match event
Counter borrow event (period match) or duty match event
(6) Multiple channels can be set to start up at an external trigger, or to restart during operation.
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