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參數(shù)資料
| 型號： | MB90F334APMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-120 |
| 文件頁數(shù)： | 74/120頁 |
| 文件大小： | 1210K |
| 代理商： | MB90F334APMC |
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MB90330A Series
57
7.
UART
UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop syn-
chronization) communications with external devices. It supports bi-directional communication (normal mode)
and master/slave communication (multi-processor mode: supported on master side only). An interrupt can be
generated upon completion of reception, detection of a reception error, or completion of transmission. EI2OS is
supported.
UART functions
UART, or a generic serial data communication interface that sends and receives serial data to and from other
CPU and peripherals, has the functions listed in following.
Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.
UART operation modes
: Setting disabled
*1 :
+ 1 is an address/data setting bit (A/D) which is used for communication control.
*2 : Only one bit can be detected as a stop bit at reception.
Operation mode
Data length
Synchronization
Stop bit length
Without parity
With parity
0
Normal mode
7-bit or 8-bit
Asynchronous
1-bit or 2-bit *2
1
Multi processor mode
8-bit
+ 1*1
Asynchronous
2
Normal mode
1 to 8-bit
Synchronous
No
Function
Data buffer
Full-duplex double-buffered
Transmission mode
Clock synchronous (without start/stop bit)
Clock asynchronous (start-stop synchronous)
Baud rate
Special-purpose baud-rate generator
It is optional from 8 kinds.
Baud rate by external clock (SCK0/SCK1/SCK2/SCK3 terminal input)
Data length
8-bit or 7-bit (in the asynchronous normal mode only)
1-bit to 8-bit (synchronous mode only)
Signal system
Non Return to Zero (NRZ) system
Reception error detection
Framing error
Overrun error
Parity error (Not supported in operation mode 1)
Interrupt request
Receive interrupt (reception completed, reception error detected)
Transmission interrupt (transmission completed)
Both the transmission and reception support EI2OS.
Master/slave type
communication function
(multi processor mode)
Capable of 1 (master) to many (slaves) communication (available just as master)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90F334APMC1-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC1-G-SPE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC-G-SNE1 | 制造商:FUJITSU 功能描述: |
| MB90F334APMC-G-SPE1 | 制造商:FUJITSU 功能描述: |
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