參數(shù)資料
型號(hào)： MB90980
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專(zhuān)有
文件頁(yè)數(shù)： 31/48頁(yè)
文件大小： 321K
代理商： MB90980
MB90980 Series
31
3.6
2.7
3.0
4
1.5
16
25
16
12
25
24
8
6
4
34
8
12.5
16
25
20
32
50
20
18
1.5
9
56
10
40
Range of warranted PLL operation
Normal operating range
S
C
Internal clock f
CP
(MHz)
Internal operating clock frequency vs. Power supply voltage
Base oscillator frequency vs. Internal operating clock frequency
Base oscillator clock F
CH
(MHz)
I
C
Range of warranted PLL operation
Notes:
Only at 1 multiplied PLL, use with more than f
CP
=
4 MHz.
For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”.
No multiplied
*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < f
CP
≤
25 MHz, set
the PLLOS register to “DIV2 bit
=
1” and “PLL2 bit
=
1”.
[Example]
When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :
CKSCR register : CS1 bit
=
“0”, CS0 bit
=
“0”
[Example]
When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :
CKSCR register : CS1 bit
=
“1”, CS0 bit
=
“0”
*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < f
CP
≤
25 MHz, the following
setting is also enabled.
2 multiplied PLL : CKSCR register : CS1 bit
=
“0”, CS0 bit
=
“0”
PLLOS register : DIV2 bit
=
“0”, PLL2 bit
=
“1”
4 multiplied PLL : CKSCR register : CS1 bit
=
“0”, CS0 bit
=
“1”
PLLOS register : DIV2 bit
=
“0”, PLL2 bit
=
“1”
*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit
=
0” and “PLL2 bit
=
1”.
[Example]
When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :
CKSCR register : CS1 bit
=
“1”, CS0 bit
=
“0”
[Example]
When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :
CKSCR register : CS1 bit
=
“1”, CS0 bit
=
“1”
PLLOS register : DIV2 bit
=
“1”, PLL2 bit
=
“1”
PLLOS register : DIV2 bit
=
“1”, PLL2 bit
=
“1”
PLLOS register : DIV2 bit
=
“0”, PLL2 bit
=
“1”
PLLOS register : DIV2 bit
=
“0”, PLL2 bit
=
“1”
×
1*
1
×
2*
1,
*
2
×
3*
1
×
4
*
1,
*
2
×
6*
3
×
8*
3
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