
MB90980 Series
19
(Continued)
Address
Abbreviated
register name
Register name
R/W
Resource name
Initial value
00004A
H
00004B
H
00004C
H
00004D
H
00004E
H
00004F
H
000050
H
000051
H
000052
H
to
000055
H
OCCP0
Output compare register (ch.0) lower digits
Output compare register (ch.0) upper digits
Output compare register (ch.1) lower digits
Output compare register (ch.1) upper digits
Output compare register (ch.2) lower digits
Output compare register (ch.2) upper digits
Output compare register (ch.3) lower digits
Output compare register (ch.3) upper digits
R/W
16-bit I/O timer
output compare
(ch.0 to ch.3)
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
OCCP1
R/W
OCCP2
R/W
OCCP3
R/W
Reserved area
000056
H
OCS01
Output compare control register (ch.0, ch.1)
lower digits
Output compare control register (ch.0, ch.1)
upper digits
Output compare control register (ch.2, ch.3)
lower digits
Output compare control register (ch.2, ch.3)
upper digits
R/W
16-bit I/O timer
output compare
(ch.0 to ch.3)
0 0 0 0 - - 0 0
B
000057
H
R/W
- - - 0 0 0 0 0
B
000058
H
OCS23
R/W
0 0 0 0 - - 0 0
B
000059
H
R/W
- - - 0 0 0 0 0
B
00005A
H
,
00005B
H
00005C
H
00005D
H
00005E
H
00005F
H
000060
H
000061
H
000062
H
000063
H
000064
H
000065
H
000066
H
000067
H
000068
H
000069
H
00006A
H
00006B
H
Reserved area
IPCP0
Input capture data register (ch.0) lower digits
Input capture data register (ch.0) upper digits
Input capture data register (ch.1) lower digits
Input capture data register (ch.1) upper digits
Input capture control status register
R
R
R
R
16-bit I/O timer
input capture
(ch.0, ch.1)
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
IPCP1
ICS01
R/W
Reserved area
TCDT
TCDT
TCCS
TCCS
Timer counter data register lower digits
Timer counter data register upper digits
Timer counter control status register
Timer counter control status register
Compare clear register lower digits
Compare clear register upper digits
Up/down count register (ch.0)
Up/down count register (ch.1)
Reload/compare register (ch.0)
Reload/compare register (ch.1)
R/W
R/W
R/W
R/W
16-bit I/O timer
free-run timer
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 - - 0 0 0 0 0
B
XXXXXXXX
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
CPCLR
R/W
UDCR0
UDCR1
RCR0
RCR1
R
R
W
W
W,
R/W
R/W
8/16-bit up/
down counter/
timer
00006C
H
CCRL0
Counter control register (ch.0) lower digits
0 X 0 0 X 0 0 0
B
00006D
H
CCRH0
Counter control register (ch.0) upper digits
0 0 0 0 0 0 0 0
B