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參數資料
| 型號： | MB90583CA |
| 廠商： | Fujitsu Limited |
| 英文描述： | Octal Bus Transceivers With 3-State Outputs 20-CDIP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數： | 70/124頁 |
| 文件大?。?/td> | 2639K |
| 代理商： | MB90583CA |
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MB90580C Series
70
18. Address Match Detection Function
When an address matches the value set in the address detection register, the instruction code to be loaded into
the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the
CPU executes the INT9 instruction. The address match detection function is implemented by processing using
the INT9 interrupt routine.
The device contains two address detection registers, each provided with a compare enable bit. When the value
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
Program address detection register 0 to 2 (PADR0)
bit
PADR0 (lower)
Address
: 001FF0
H
Access
Initial value
bit
PADR0 (middle) Address
: 001FF1
H
Access
Initial value
bit
PADR0 (upper)
Address
: 001FF2
H
Access
Initial value
Program address detection register 3 to 5 (PADR1)
bit
PADR1 (lower)
Address
: 001FF3
H
Access
Initial value
bit
PADR1 (middle) Address
: 001FF4
H
Access
Initial value
bit
PADR1 (upper)
Address
: 001FF5
H
Access
Initial value
Program address detection control/status register (PACSR)
bit
7
6
5
4
3
2
1
0
Address
: 00009E
H
Re-
served
(
)
(0)
Re-
served
(
)
(0)
Re-
served
(
)
(0)
Re-
servedAD1E
(
) (R/W) (
) (R/W) (
)
(0)
(0)
(0)
Re-
servedAD0E
Re-
served
Access
Initial value
(0)
(0)
7
6
5
4
3
2
1
0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
17
16
15
14
13
12
11
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
17
16
15
14
13
12
11
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
17
16
15
14
13
12
11
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
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