參數(shù)資料
型號(hào): MB90583CA
廠商: Fujitsu Limited
英文描述: Octal Bus Transceivers With 3-State Outputs 20-CDIP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 58/124頁
文件大?。?/td> 2639K
代理商: MB90583CA
MB90580C Series
58
12. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features.
Conversion time: Minimum of 34.7
μ
s per channel (for a 12 MHz machine clock)
Uses RC-type successive approximation conversion with a sample and hold circuit.
8/10-bit resolution
Eight program-selectable analog input channels
Single conversion mode: Selectively convert one channel.
Scan conversion mode: Continuously convert multiple channels. Maximum of 8 program selectable channels.
Continuous conversion mode : Repeatedly convert specified channels.
Stop conversion mode:Convert one channel then halt until the next activation. (Enables synchronization of the
conversion start timing.)
An A/D conversion completion interrupt request.
An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate EI
2
OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register configuration
Control status register (upper)
bit
15
14
13
12
11
10
9
8
Address
: 000037
H
BUSY INT INTE PAUS STS1 STS0 STRT
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (
)
(0)
(0)
(0)
(0)
Re-
served
ADCS2
Access
Initial value
(0)
(0)
(0)
(0)
Control status register (lower)
bit
7
6
5
4
3
2
1
0
Address
: 000036
H
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
ADCS1
Access
Initial value
(0)
(0)
(0)
(0)
Data register (upper)
bit
15
14
13
ST0
12
CT1
11
CT0
10
9
8
Address
: 000039
H
SELB ST1
(W) (W) (W) (W) (W) (
) (R) (R)
(0)
(0)
(0)
(0)
D9
D8
ADCR2
Access
Initial value
(1) (
) (X)
(X)
Data register (lower)
bit
7
6
5
4
3
2
1
0
Address
: 000038
H
D7
(R) (R) (R) (R) (R) (R) (R) (R)
(X)
(X)
(X)
(X)
D6
D5
D4
D3
D2
D1
D0
ADCR1
Access
Initial value
(X)
(X)
(X)
(X)
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