參數(shù)資料
型號(hào)： MB90522PFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： Quadruple 2-Input Positive-NAND Gates 14-CFP -55 to 125
中文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁數(shù)： 74/106頁
文件大小： 1539K
代理商： MB90522PFV
MB90520 Series
74
18. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1,” the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
Program address detection register 0 to 2 (PADR0)
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
Initial value
XXXXXXXX
B
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
Address
PADR0 (High order address) : 001FF2
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXX
B
Address
PADR0 (Middle order address) : 001FF1
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR0 (Low order address) : 001FF0
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
Initial value
XXXXXXXX
B
Address
PADR1 (High order address) : 001FF5
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXX
B
Address
PADR1 (Middle order address) : 001FF4
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR1 (Low order address) : 001FF3
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
B
Address
00009E
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program address detection register 3 to 5 (PADR1)
Program address detection control status register (PACSR)
Reserved
AD1E
Reserved
AD0E
Reserved
Reserved Reserved Reserved
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