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參數(shù)資料
| 型號(hào)： | MB90522PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Quadruple 2-Input Positive-NAND Gates 14-CFP -55 to 125 |
| 中文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 43/106頁(yè) |
| 文件大?。?/td> | 1539K |
| 代理商： | MB90522PFV |
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MB90520 Series
43
Block diagram of 8/16-bit PPG timer 1
PPG1 underflow
(to PPG0)
*
: Interrupt number
HCLK: Oscillation clock frequency
φ
: Machine clock frequency
PRLH0
PEN1
Data bus for “H” digits
Data bus for “L” digits
PPG1 operating mode
control register (PPGC1)
PRLL0
Temporary buffer
(PRLBH1)
Re-load selector
(L/H selector)
Down counter
(PCNT1)
PPG1
output latch
Pin
Count value
Clear
2
Select signal
Re-load
Underflow
Reverse
PPG output control circuit
MD0
P40/PG10
Count clock selector
Select signal
PPG1 re-load
register
Operating
mode
control signal
PPG0 underflow
CLK
Interrupt
request
#23*
Timebase timer output (512/HCLK)
Peripheral clock (16/
φ
)
Peripheral clock (8/
φ
)
Peripheral clock (4/
φ
)
Peripheral clock (2/
φ
)
Peripheral clock (1/
φ
)
—
PEI0
PIE1 PUF1 MD1
MD0
Reserved
R
S
Q
Pin
P41/PG11
PCS2
3
PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG0, 1 Output control register (PPGOE0, 1)
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