
MB90495G Series
48
DS07-13713-6E
Block Diagram of 8/16-Bit PPG Timer1
PPG1
CLK
MD0
R
S
Q
PEN1
PE1
PIE1 PUF1 MD1
MD0
PCS2
PCS0 PCM2 PCM1 PCM0
PCS1
3
2
PPG1 reload
register
Operation
mode control signal
PPG1 underflow
(to PPG0)
PPG0 underflow
(from PPG0)
PRLH1
("H" side)
PPG1 temporary
buffer (PRLBH1)
Reload selector
L/H selector
Initial count value
PPG1 down counter
(PCNT1)
PRLL1
("L" side)
Reload
Underflow
Time-base timer output
(512/HCLK)
Peripheral clock (1/
φ)
Peripheral clock (2/
φ)
Peripheral clock (4/
φ)
Peripheral clock (8/
φ)
Peripheral clock (16/
φ)
Select signal
Clear
Invert
PPG1
output latch
PPG output control circuit
Select signal
Counter
clock
selector
PPG0/1 count clock selection register (PPG01)
"H" level side data bus
"L" level side data bus
PPG1 operation mode control register
(PPGC1)
Re-
served
Output
interrupt
request*
Pin
:
Undefined
Reserved : Reserved bit
HCLK
:
Oscillation clock frequency
φ
:
Machine clock frequency
*
: Interrupt output from 8/16-bit PPG timer 1 is merged with interrupt request output from
PPG timer 0 into a single interrupt via an OR circuit.