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參數(shù)資料
| 型號(hào)： | MB90440G |
| 廠商： | Fujitsu Limited |
| 英文描述： | Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 49/61頁(yè) |
| 文件大?。?/td> | 644K |
| 代理商： | MB90440G |
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MB90440G Series
49
(9) UART0/1, Serial I/O Timing
(V
CC
=
4.5 V to 5.5 V, V
SS
=
0.0 V, T
A
=
40
°
C to
+
105
°
C)
Value
Notes :
AC ratings in CLK synchronous mode.
C
L
is load capacitance value connected to pins when testing.
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
Serial clock cycle time
t
SCYC
SCK0 to
SCK2
An output pin of
internal sift clock
mode
C
L
=
80 pF
+
1 TTL.
8 t
CP
ns
SCK
↓
→
SOT delay time
t
SLOV
SCK0 to
SCK2,
SOT0 to
SOT2
–80
+
80
ns
Valid SIN
→
SCK
↑
t
IVSH
SCK0 to
SCK2,
SIN0 to SIN2
100
ns
SCK
↑
→
valid SIN hold time
t
SHIX
SCK0 to
SCK2,
SIN0 to SIN2
60
ns
Serial clock “H” pulse width
t
SHSL
SCK0 to
SCK2
An output pin of
external sift clock
mode
C
L
=
80 pF
+
1 TTL.
4 t
CP
ns
Serial clock “L” pulse width
t
SLSH
SCK0 to
SCK2
4 t
CP
ns
SCK
↓
→
SOT delay time
t
SLOV
SCK0 to
SCK2,
SOT0 to
SOT2
150
ns
Valid SIN
→
SCK
↑
t
IVSH
SCK0 to
SCK2,
SIN0 to SIN2
60
ns
SCK
↑
→
valid SIN hold time
t
SHIX
SCK0 to
SCK2,
SIN0 to SIN2
60
ns
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