參數(shù)資料
型號(hào)： MB90440G
廠商： Fujitsu Limited
英文描述： Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-CDIP -55 to 125
中文描述： 16位微控制器專有
文件頁數(shù)： 2/61頁
文件大?。?/td> 644K
代理商： MB90440G
MB90440G Series
2
I
FEATURES
Clock
Internal PLL clock multiplication circuit
Base oscillation divided into two or multiplied by one to four
Minimum execution time : 62.5 ns (4 MHz oscillation, PLL clock multiplication multiplier
=
4, V
CC
=
5.0 V)
32 kHz subsystem clock
Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
Singed multiplication/division and extended RET1 instructions
32-bit accumulator enhancing high-precision operations
Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
Program patch function (for two address pointers)
Enhanced execution speed : 4 byte instruction queue
Enhanced interrupt function : 8 priority levels programmable and 34 causes
Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
2
OS)
Internal ROM size and type
FLASH ROM : 128 Kbytes
Internal RAM size : 6 Kbyte and 14 Kbyte (evaluation chip)
FLASH ROM
Supports automatic programming function, Embedded Algorithm*
Writing command/erase command/erase suspend and resume command
Algorithms completion flag
Hardwire reset vector to show the fixed boot code sector
Can be erased by each sector
Sector protection by external programming voltage
Low-power consumption (stand-by) modes
Sleep mode (CPU operating clock stops)
Stop mode (Main oscillation stops)
CPU intermittent operation mode
Watch mode
Time-base timer mode
General-purpose I/O ports : 81 ports
Timers
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit
×
4 channels
16-bit reload timer : 2 channels
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(Continued)
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