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| 型號(hào)： | MB90246APFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 91/100頁(yè) |
| 文件大小： | 1959K |
| 代理商： | MB90246APFV |
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90
MB90246A Series
Table 15
Logic 2 (Long) [6 Instructions]
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 16
Sign Reverse (Byte, Word) [6 Instructions]
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 17
Absolute Values (Byte, Word, Long) [3 Instructions]
Table 18
Normalize Instruction (Long) [1 Instruction]
* : Set to 5 when the accumulator is all “0”, otherwise set to 5 + (R0).
Mnemonic
#
~
B
Operation
LH AH
IS
T
N
Z
V
C RMW
ANDL
A, ear
ANDL
A, eam
ORL
A, ear
ORL
A, eam
XORL
A, ear
XORL
A, eam
2
2 +
2
2 +
2
2 +
5
6 + (a)
5
6 + (a)
5
6 + (a)
0
(d)
0
(d)
0
(d)
long (A)
← (A) and (ear)
long (A)
← (A) and (eam)
long (A)
← (A) or (ear)
long (A)
← (A) or (eam)
long (A)
← (A) xor (ear)
long (A)
← (A) xor (eam)
–
*
R
–
Mnemonic
#
~
RG
BOperation
LH AH
IS
T
N
Z
V
C RMW
NEG
A
NEG
ear
NEG
eam
1
2
2 +
2
3
5 + (a)
0
2
0
2
× (b)
byte (A)
← 0 – (A)
byte (ear)
← 0 – (ear)
byte (eam)
← 0 – (eam)
X
–
*
–
*
NEGW A
NEGW ear
NEGW eam
1
2
2 +
2
3
5 + (a)
0
2
0
2
× (c)
word (A)
← 0 – (A)
word (ear)
← 0 – (ear)
word (eam)
← 0 – (eam)
–
*
–
*
Mnemonic
#
~
B
Operation
LH AH
IS
T
N
Z
V
C RMW
ABS
A
ABSW
A
ABSL
A
2
4
0
byte (A)
← Absolute value (A)
word (A)
← Absolute value (A)
long (A)
← Absolute value (A)
Z
–
*
–
Mnemonic
#
~
RG
B
Operation
LH AH
IS
T
N
Z
V
C RMW
NRML
A, R0
2
*1
1
0
long (A)
← Shift to where “1”
is originally located
byte (R0)
← Number of shifts
in the operation
––––––
*
–
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