參數(shù)資料
型號(hào)： MB90246APFV
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁(yè)數(shù)： 67/100頁(yè)
文件大?。?/td> 1959K
代理商： MB90246APFV
69
MB90246A Series
(8) Hold Timing
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30
°C to +70°C)
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
(9)
UART Timing
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30
°C to +70°C)
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Notes: These are AC ratings in the CLK synchronous mode.
CL is the load capacitor value connected to pins while testing.
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min.
Max.
Pins in floating status
→
HAK
↓ time
tXHAL
HAK
VCC = 5.0 V
±10%
30
1 tCYC*ns
HAK
↑ → pin valid time tHAHV
HAK
—1 tCYC*2 tCYC*ns
Parameter
Symbol Pin name
Condition
Value
Unit
Remarks
Min.
Max.
Serial clock cycle time
tSCYC
SCK0
—
8 tCYC*—
ns
Internal shift
clock mode
CL = 80 pF for
an output pin
SCK
↓ → SOD delay
time
tSLOV
SCK0,
SOD0
VCC = 5.0 V
±10%
–80
80
ns
Valid SID
→ SCK ↑
tIVSH
SCK0,
SID0
100
—
ns
SCK
↑ → valid SID hold
time
tSHIX
SCK0,
SID0
60
—
ns
Serial clock “H” pulse
width
tSHSL
SCK0
—
4 tCYC*—
ns
External shift
clock mode
CL = 80 pF for
an output pin
Serial clock “L” pulse
width
tSLSH
SCK0
4 tCYC*—
ns
SCK
↓ → SOD delay
time
tSLOV
SCK0,
SID0
VCC = 5.0 V
±10%
—
150
ns
Valid SID
→ SCK ↑
tIVSH
—60
—
ns
SCK
↑ → valid SID hold
time
tSHIX
SCK0,
SID0
60
—
ns
Pins
HAK
High impedance
tXHAL
tHAHV
0.8 V
2.4 V
HRQ
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