參數(shù)資料
型號: MB90246APFV
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 43/100頁
文件大小: 1959K
代理商: MB90246APFV
47
MB90246A Series
10. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a real-
time operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
(2) Block Diagram
Delayed interrupt factor generation/cancellation register (DIRR)
Address
00009FH
bit 7
bit 0
————
R0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
............
(System reservation area)
————
R/W
Initial value
------- 0 B
R/W : Readable and writable
— : Unused
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt signal
S factor
R latch
——
———
R0
Internal data bus
Interrupt request signal
#42 (2AH)*
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