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參數(shù)資料
| 型號(hào)： | MB90234PFV-XXX |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 16/83頁(yè) |
| 文件大?。?/td> | 1566K |
| 代理商： | MB90234PFV-XXX |
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23
MB90230 Series
(Continued)
Address
Register
name
Access
Resouce
name
Initial value
70H
Capture register 0
ICP0
R/W
Input capture 0,
1
XXXXXXXX
71H
XXXXXXXX
72H
Capture register 1
ICP1
R/W
XXXXXXXX
73H
XXXXXXXX
74H
Control status register 0, 1
ICS0
R/W
0 0 0 0 0 0 0 0
75H to
77H
Reserved area
—
78H
Capture register 2
ICP2
R/W
Input capture 2,
3
XXXXXXXX
79H
XXXXXXXX
7AH
Capture register 3
ICP3
R/W
XXXXXXXX
7BH
XXXXXXXX
7CH
Control status register 2, 3
ICS1
R/W
0 0 0 0 0 0 0 0
7DH to
7FH
Reserved area
—
80H
OP code register
EOPC
R/W
Serial E2PROM
interface
––––0000
81H
Format status register
ECTS
R/W
0 0 0 0 0 0 0 0
82H
Data register
EDAT
R/W
X XXXXXXX
83H
XXXXXXXX
84H
Address register
EADR
R/W
0 0 0 0 0 0 0 0
85H
00–––000
86H to
8FH
Reserved area
—
90H to
9EH
System reserved area
—
*1
—
9FH
Delayed interrupt source generate/
release register
DIRR
R/W
Delayed interrupt
generation module
–––––––0
A0H
Standby control register
STBYC
R/W
Low-power
consumption
mode
0001X X X X
A1H
Reserved area
—
A2H
Reserved area
—
A3H
Middle address control register
MACR
W
External pin
*2
A4H
Upper address control register
HACR
W
External pin
*2
A5H
External pin control register
EPCR
W
External pin
*2
A6H
Reserved area
—
A7H
Reserved area
—
A8H
Watchdog timer control register
TWC
R/W
Watchdog timer/
reset
XXXXXXXX
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