參數(shù)資料
型號(hào)： MB90050PF
廠商： FUJITSU LTD
元件分類： 顯示控制器
英文描述： On-Screen Display Controller
中文描述： 35 X 16 CHARACTERS CRT CHAR OR GRPH DSPL CTLR, PQFP48
封裝： PLASTIC, QFP-48
文件頁(yè)數(shù)： 7/41頁(yè)
文件大小： 743K
代理商： MB90050PF
MB90050
7
(Continued)
Pin
no.
Pin
name
I/O
Circuit
type
Function
28
DCLKO
O
G
Dot clock signal output pin.
This pin outputs an LC oscillation clock signal.
The pin enables output (ON/OFF) control depending on the command setting.
The normal clock (that stops oscillation during horizontal synchronization) or con-
tinuous clock (that does not stop oscillation during horizontal synchronization*)
can be command-selected for the output using the command setting for output se-
lection control (CKS).
When the TESTI2 pin inputs a low level signal, this pin outputs the continuous
clock signal that does not stop oscillation during horizontal synchronization
(where the output selection control (CKS) setting is disabled).
When the RESET pin inputs the low level signal, the pin outputs a dot clock signal.
* : For continuous clock, this pin is used for frequency measurement. To measure
the dot clock, the pin sets display signal output that is not the standard and
cannot display correctly.
Crystal oscillator 4FSC clock signal output pin.
This pin enables output (ON/OFF) control depending on the command setting.
The crystal oscillation clock (4FSC) or its 1/4 frequency clock (FSC) can be com-
mand-selected for the output using the command setting for output selection con-
trol (FSS).
When the TESTI2 pin inputs the low level signal, this pin outputs the 4FSC clock
signal (where the output selection control (FSS) setting is disabled).
When the RESET pin inputs the low level signal, this pin outputs the 4FSC clock
signal.
Halftone display period signal output pin.
This pin enables output (ON/OFF) control and output logic control depending on
the command setting.
When the RESET pin inputs the low level signal, this pin sets the output to OFF
(output tied to the low).
(The input feature of the pin is a test function. Use the pin usually only for output.)
Display period signal output pin.
This pin enables output (ON/OFF) control and output logic control depending on
the command setting. When the RESET pin inputs the low level signal, this pin
sets the output to OFF (entering the low level signal fixed output state).
(The input feature of the pin is a test function. Use the pin usually only for output.)
8
FSC4O
O
G
26
DH
O (I)
H
27
DB
O (I)
H
34,
33,
32,
31,
30,
29
DCOL5,
DCOL4,
DCOL3,
DCOL2,
DCOL1,
DCOL0
O (I)
H
Display color signal output pin.
This pin enables output (ON/OFF) control and output logic control depending on
the command setting. When the RESET pin inputs the low level signal, this pin
sets the output to OFF (entering the low level signal fixed output state).
(The input feature of the pin is a test function. Use the pin usually only for output.)
36,
35,
24,
23
PO3,
PO2,
PO1,
PO0
O (I)
H
Port signal output pin.
This pin enables output level (High/Low) control depending on the command set-
ting. When the RESET pin inputs the low level signal, this pin sets the output to
OFF (entering the low level signal fixed output state).
(The input feature of the pin is a test function. Use the pin usually only for output.)
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