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參數(shù)資料
| 型號： | MB90050PF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | On-Screen Display Controller |
| 中文描述： | 35 X 16 CHARACTERS CRT CHAR OR GRPH DSPL CTLR, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 6/41頁 |
| 文件大小： | 743K |
| 代理商： | MB90050PF |
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MB90050
6
(Continued)
Pin
no.
Pin
name
I/O
Circuit
type
Function
9
VSYNCO
O
F
Vertical sync signal output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the high).
10
HSYNCO
O
F
Horizontal sync signal output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the high).
11
CSYNCO
O
F
Composite sync signal output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the high).
12
VBLKO
O
F
Vertical blanking interval (VBI) output pin.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the low).
13
FLDO
O
F
Field signal output pin.
During operation under internal synchronization control, this pin outputs the in-
ternally generated field signal.
During operation under external synchronization control, the pin outputs the
field signal (internally detected field signal or external input field signal) used for
internal operations.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the low).
14
SYNCST
O
F
Synchronization detection signal output pin.
This pin outputs a significant level signal with a sync signal detected and an in-
significant level signal with no sync signal detected.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs the low level signal, this pin turns off the internal
pull-up resistor and sets the output to OFF (output tied to the low).
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