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參數(shù)資料
| 型號： | MB90050PF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | On-Screen Display Controller |
| 中文描述： | 35 X 16 CHARACTERS CRT CHAR OR GRPH DSPL CTLR, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 5/41頁 |
| 文件大?。?/td> | 743K |
| 代理商： | MB90050PF |
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MB90050
5
■
PIN DESCRIPTIONS
(Continued)
Pin
no.
Pin name I/O
Circuit
type
Function
6,
7
EXS,
XS
I/O
A
Crystal oscillation circuit pins for color burst clock generator.
Connect an external crystal oscillator (14.31818 MHz for NTSC or 17.734475
MHz for PAL) and load capacitance (C) to these pins to form a crystal oscillation
circuit.
LC oscillation circuit pins for display dot clock generator.
Connect these pins to external “L” and “C” to from an LC oscillation circuit.
Chip select signal input pin.
For serial command transfer, set this pin to the Low level.
Serial clock signal input pin.
This pin feeds a clock signal upon transfer of a serial command. It feeds serial
data at the rising edge.
Serial data signal input pin.
Input data during serial command transfer.
Busy signal output pin.
This pin outputs a significant level signal during VRAM filling. Do not input a
serial command while the pin outputs the significant level signal.
Supplying a low level signal to the CS pin during the significant level signal out-
put period terminates the VRAM fill operation and causes this pin to output an
insignificant level signal.
The pin enables output (ON/OFF) control, output logic control, and internal pull-
up ON/OFF control depending on the command setting.
When the RESET pin inputs a low level signal, this pin outputs the busy signal,
turns off the internal pull-up resistor, and sets the output to OFF (output tied to
the low).
Vertical sync signal input pin.
Active low signal or active high signal input is command-selectable for the pin.
When the RESET pin inputs the low level signal, this pin inputs the active low
signal.
Horizontal sync signal input pin.
Active low signal or active high signal input is command-selectable for the pin.
When the RESET pin inputs the low level signal, this pin inputs the active low,
horizontal sync signal.
Field signal input pin.
The internal field signal identically detected from among input sync signals or the
input signal to this pin is command-selectable for field control.
During operation under external synchronization control, the input signal is used
to control the least significant bit of the font ROM/RAM raster address.
The input signal to this pin is disabled during operation under internal synchro-
nization control.
20,
19
EXD,
XD
I/O
B
15
CS
I
C
16
SCLK
I
C
17
SIN
I
C
18
BUSY
O
F
2
VSYNCI
I
D
3
HSYNCI
I
D
1
FLDI
I
D
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