參數(shù)資料
型號: MB86967
廠商: Fujitsu Limited
英文描述: LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
中文描述: 局域網(wǎng)控制器與PC卡,ISA總線和通用總線接口
文件頁數(shù): 38/129頁
文件大?。?/td> 1499K
代理商: MB86967
38
MB86967
(2) DLCR1: Receive Status Register
DLCR1 indicates the receive status of the data link controller. The external interrupt INT is asserted by setting
the bits of DLCR3 corresponding to the status bits, bit 7 to 0.
(Continued)
Bit 7
Bit 6
BUS RD
ERR
BIT CLR
0
Bit 5
DMA
EOP
BIT CLR
0
Bit 4
Bit 3
RX SRT
PKT
BIT CLR
0
Bit 2
Bit 1
Bit 0
Read
PKT RDY
RMT RST
ALG ERR CRC ERR OVRFLO
Write
BIT CLR
0
BIT CLR
0
BIT CLR
0
BIT CLR
0
BIT CLR
0
Initial Value
Bit no.
7
Bit name
PKT RDY
(Packet Ready)
Operation
Read
Value
0
1
Function
No received packet is in the receiver buffer.
Indicates packets from self office received normally and
transferred completely to receiver buffer.
In other words, at least one packet of receive data is in the
receiver buffer.
Not affected
This bit is cleared. If there are still received packets in the
receiver buffer even after the host system has read one
packet of receive data from the receiver buffer, this bit is
automatically reset.
No bus read error
Indicates LSI failed to assert RDY signal within 2.15
μ
s at
reading data in receiver buffer from host system.
In other words, the host system attempted to read data from
the receiver buffer, although the buffer has no data to read.
Not affected
This bit is cleared.
Indicates DMA transfer not yet
completed during DMA transfer.
This bit is cleared when both the
DMA RENA and DMA TENA bits of
the BMPR12 are cleared.
Indicates DMA transfer completed
and EOP signal asserted by
external DMA controller
Not affected
This bit is cleared. This clearing
should be done by clearing both the
DMA RENA and DMA TENA bits of
the BMPR12.
Write
0
1
6
BUS RD ERR
(Bus Read
Error)
Read
0
1
Write
0
1
0
5
DMA EOP
Read
* :This bit is invalid in the
PC card mode.
1
Write
0
1
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