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參數(shù)資料
| 型號： | MB86967 |
| 廠商： | Fujitsu Limited |
| 英文描述： | LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| 中文描述： | 局域網(wǎng)控制器與PC卡，ISA總線和通用總線接口 |
| 文件頁數(shù)： | 10/129頁 |
| 文件大?。?/td> | 1499K |
| 代理商： | MB86967 |
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10
MB86967
System interface pins in general-purpose mode
(Continued)
Pin no.
18 to 23,
25,
27 to 29,
85,
87 to 91
4 to 7
Symbol
SD0 to SD15
Pin name
I/O
BD
Function
SYSTEM DATA BUS
These pins are used as a data bus for data exchange
between the host system and the MB86967. They
are also used for DMA transfer. In the 8-bit bus mode
(bit 5 of DLCR6 = 1), only the 8 lower bits (SD0 to
SD7) are used.
These pins are used for input of system address
signals for selecting MB86967 registers, BOOT
PROM, and ID PROM.
This pin is used for input of Active-Low chip select
signals.
ISU This pin is used for input of hardware reset signals
(Active High).
IU
This pin is used for input of I/O read strobe signals
(Active Low).
IU
This pin is used for input of I/O write strobe signals
(Active Low).
ID
This pin is used for input of signals indicating the end
of DMA transfer between the buffer memory and host
system. At EOP input, the next DREQ is not output
and the handshaking cycle is terminated. Either
Active High or Active Low can be selected.
ID
This pin is used for input of Active-Low signals and
for connection of DMAC acknowledge signals
indicating that the DMAC is read for transmitting and
receiving data to and from buffer memory.
ID
This pin is used for input of Active-Low signals and
for controlling byte/word transfer. In the 16-bit data
bus mode (bit 5 (SB/SW)of DLCR6 = 0), this pin,
together with SA0, controls word transfer and the
transfer of upper and lower bytes on the data bus.
SA0 to SA3
SYSTEM ADDRESS
BUS
ID
82
ECS
ENABLE CHIP
SELECT
CHIP RESET
IU
64
HWRST
15
IOR
I/O READ
17
IOW
I/O WRITE
13
EOP
END OF PROCESS
12
DMACK
DMA
ACKNOWLEDGE
11
BHE
SYSTEM BUS HIGH
ENABLE
×
: don’t care
This pin is used for output of Active-Low interrupt
request signals.
This pin is used for input of DMA transfer request
signals.
92
INT
INTERRUPT
REQUEST
DMA REQUEST
(Active High)
O
2
DREQ
O
SB/SW
0
SBHE
0
SA0
0
Function
Word transfer
Transfer of upper bytes on
data bus (SD15 to SD8)
Transfer of lower bytes on
data bus (SD7 to SD0)
Unused
Byte transfer
(SD7 to SD0)
0
0
1
0
1
0
0
1
1
1
×
×
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PDF描述 |
|---|---|
| MB86967PFV | LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86977 | IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | IP PACKET FORWARDING ENGINE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
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