參數(shù)資料
型號: MB86942PFV
廠商: FUJITSU LTD
元件分類: 外設及接口
英文描述: Peripheral LSI for SPARClite
中文描述: MULTIFUNCTION PERIPHERAL, PQFP144
封裝: PLASTIC, QFP-144
文件頁數(shù): 9/49頁
文件大?。?/td> 598K
代理商: MB86942PFV
9
MB86941/942
2. INTERRUPT REQUESTS (15)
Pin symbol
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Pin no.
23
22
15
14
13
12
6
5
4
3
2
144
143
142
141
Pin name
Description
Interrupt Request 1
Interrupt Request 2
Interrupt Request 3
Interrupt Request 4
Interrupt Request 5
Interrupt Request 6
Interrupt Request 7
Interrupt Request 8
Interrupt Request 9
Interrupt Request 10
Interrupt Request 11
Interrupt Request 12
Interrupt Request 13
Interrupt Request 14
Interrupt Request 15
Interrupt request pin
Interrupt receiving priority: IRQ15 is highest priority
and IRQ1 is lowest.
A choice of four interrupt waveforms is available by
mode setting for each of the 15 pins independently,
including “H” level, “L” level, rising edge, and falling
edge.
Each input has a filtering function for short pulse
signals, by which an interrupt request is recognized
once a signal is detected at active level at three
successive rising edges of the internal clock signal.
Once an interrupt request is detected, it passes
through priority control and masking control and is
output at the IRL<3:0> pins as an interrupt request to
the MPU.
If these pins are not used, they should be fixed at
inactive level.
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