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參數(shù)資料
| 型號(hào)： | MB86942PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Peripheral LSI for SPARClite |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 13/49頁 |
| 文件大?。?/td> | 598K |
| 代理商： | MB86942PFV |
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13
MB86941/942
(Continued)
Pin symbol
I/O
Pin no.
Pin name
Description
SYBRK0
I/O
32
Synchronous/Break
Detect 0
These pins can function as synchronization detect
input, synchronization detect output, or break detect
output pins, depending on the mode setting.
External synchronization mode setting:
Synchronization signals are input at these pins.
When the RCLK is “H” level and these pins receive
an “H” signal in hunting operation, the data
sampled at the next rise of RCLK is the starting bit
of the receiving data.
Internal synchronization mode:
These pins are used as the synchronization
character detect output pins. When incoming data
matches the synchronization character register
setting (both characters must match in
bisynchronous mode), an “H” signal is output
here.
Next, the status register is read and this signal
returns to “L” at the end of the read signal.
Asynchronous mode:
These pins function as break detect output pins.
Immediately after a framing error, an “H” signal is
output if all receiving data values (one frame
including start bit, parity bit, and stop bit) are “0.”
This “H” signal is cancelled if a “1” data is received
before a reset is applied.
SYBRK1
I/O
53
Synchronous/Break
Detect 1
RRDY0
O
43
Receive Ready 0
Receive Ready output pin
These pins are “H” level, when serial data received at
the RCVDT0, RCVDT1 pins is converted to parallel
data in the SDTR module and is in readable form.
Then after the received data is read, these pins
becomes “L” level at the end of the read signal.
RRDY1
O
44
Receive Ready 1
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