參數(shù)資料
型號： MB86703PF
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 31/32頁
文件大?。?/td> 189K
代理商： MB86703PF
MB86703
Plug and Play ISA Controller
8
Device Interface Signals
PIN
NUMBER
SYMBOL
TYPE
DESCRIPTION
23
24
25
26
/IOCSA
/IOCSB
/IOCSC
/IOCSD
O
I/O CHIP SELECTS: These active low outputs are assigned to different logical
devices depending on the sub-mode in which the MB86703 is operating.
Can be used by any device that requires I/O space
27
/MCSA
{DRQA}
O {I}
MEMORY CHIP SELECT A{DMA REQUEST A}: This pin is always assigned
to logical device 0 in any submode. In MEMORY mode, it is an active low output
which can be used by any device that requires memory space. In DMA mode,
it is an active high input which is asserted to indicate that the device is
requesting bus ownership to transfer data.
29
/MCSB
{/DACKA}
O
MEMORY CHIP SELECT B{DMA ACKNOWLEDGE A}: This pin is assigned
to different logical devices depending on the sub-mode in which the MB86703
is operating. In MEMORY mode, it is an active low output which can be used by
any device that requires memory space. In DMA mode, it is an active low output
which indicates that the platform is ready to proceed with the requested DMA
cycle. It is produced in response to receipt of /DACKn from the system bus.
32
NC{/
DACKB}
{O}
NO CONNECT{DMA ACKNOWLEDGE B}: Not used in MEMORY mode.
In DMA mode, this is an active low output which indicates that the platform is
ready to proceed with the requested DMA cycle. It is produced in response to
receipt of /DACKn from the system bus.
39
42
43
44
INTA
INTB
INTC
INTD
I
INTERRUPT REQUESTS: Inputs from the I/O controller which indicate that it
is requesting an interrupt. These inputs are assigned to different logical devices
depending on the submode in which the MB86703 is operating. The inputs can
be programmed to be active high or active low. See Table 12, EEPROM
addresses 0x017, 0x018, 0x019 and 0x01A.
53
ACTENA
I
ACTIVATE ENABLE: This pin, when asserted, causes the Activate bit in PnP
register 0x30 for each logical device to be set or reset on power up depending
on the value of the corresponding Activate bit in the EEPROM, address 0x01B.
If the ACTENA pin is negated, the values in the EEPROM are ignored and the
logical devices are not activated at power up or software reset. The state of the
pin has no effect on the ability of software to set the Activate bit(s) in the 0x30
registers for each logical device during the configuration process.
38
RDY
I
READY: Input from the I/O device which goes low at the beginning of a read or
write cycle and is set high when the peripheral controller is ready to complete the
requested transaction.
37
/RESET
O
BOARD RESET: An active low output to the board produced in response to
receipt of RESET_DRV on the ISA bus or if a reset command is issued by writing
a “0x07” to the Configuration Control Register, 0x02.
1, 21, 30,
41, 56, 61,
65, 72
GND
-
GROUND: Signal and power ground.
20, 40, 60,
70
VDD
-
POWER SUPPLY: +5 volts 5%.
相關PDF資料
PDF描述
MB86831-66PFV-G 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
MB86831 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller
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MB86831PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller
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