參數(shù)資料
型號(hào)： MB86703PF
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 28/32頁(yè)
文件大?。?/td> 189K
代理商： MB86703PF
Plug and Play ISA Controller
MB86703
5
LOGIC CONVENTION
Unless otherwise noted, a positive logic (active high) convention is assumed throughout this document, whereby
the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A preced-
ing slash, e.g., /RESET, indicates that the signal is asserted in a low state (nominally 0 volts). Whenever a signal is
separated into numbered bits, e.g., SD7, SD6, ..., SD0, the family of bits may also be shown collectively, e.g., as
SD<7:0>.
Some pins have different functions in MEMORY mode and in DMA mode. For those pins, the function in DMA
mode is enclosed in brackets. Dual function pins are categorized based on their function in MEMORY mode in the
tables below.
SIGNAL DESCRIPTIONS
ISA Bus Interface Signals
PIN
NUMBER
SYMBOL
TYPE
DESCRIPTION
36
RESET_DRV
I
CHIP RESET: Resets the chip and initializes internal registers and
logic. When this signal is asserted, the MB86703 enters the
Wait for
Key state.
19-4
SA<15:0>
I
SYSTEM ADDRESS: Inputs are connected to the corresponding
signals from the system bus.
80
SA16{/DACK6}
I
SYSTEM ADDRESS 16{DMA ACKNOWLEDGE 6}: In MEMORY
mode, an address input connected to the corresponding signal from
the ISA bus. In DMA mode, an active low signal from the ISA bus
indicating that a DMA acknowledge cycle is in progress.
73
75
77
79
LA17{DREQ0}
LA19{DREQ3}
LA21{DREQ5}
LA23{DREQ6}
I {O }
LATCHED ADDRESS{DMA REQUEST}: In MEMORY mode,
address inputs connected to the corresponding signal from the ISA
bus. In DMA mode, outputs indicating that the peripheral device is
ready to transfer data. Used for both read and write operations. Pins
not configured as outputs are maintained in the three-state condition.
74
76
78
LA18{/DACK0}
LA20{/DACK3}
LA22{/DACK5}
I
LATCHED ADDRESS{DMA ACKNOWLEDGE}: In MEMORY mode,
address inputs connected to the corresponding signals from the ISA
bus. In DMA mode, active low signals from the ISA bus indicating that
a DMA acknowledge cycle is in progress.
71
BALE{/DACK7}
I
BUS ADDRESS LATCH ENABLE{DMA ACKNOWLEDGE 7}: In
MEMORY mode, an active high input signal driven by the platform CPU
to indicate when the address and AEN signals are valid. In DMA mode,
an active low signal from the ISA bus indicating that a DMA
acknowledge cycle is in progress.
64-62, 59-
57, 55, 54
SD<7:0>
I/O
SYSTEM DATA: All data, command and status transfers take place
over this bus.
33
/IOR
I
I/O READ: Active low signal from the system bus which indicates that
the current bus cycle is an I/O read operation.
34
/IOW
I
I/O WRITE: Active low signal from the system bus which indicates that
the current bus cycle is an I/O write operation.
35
AEN
I
ADDRESS ENABLE: Input signal from the system bus. When low,
indicates that an I/O slave may respond to addresses and I/O
commands on the system bus.
45
46-48
49-51
52
IRQ7,
IRQ5-3,
IRQ10-12
O
INTERRUPT REQUEST: Output to the system bus which indicates
that the controller chip is requesting an interrupt. Pins not configured
as outputs are in the three-state condition.
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