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參數(shù)資料
| 型號： | MB86703PF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大小： | 189K |
| 代理商： | MB86703PF |
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MB86703
Plug and Play ISA Controller
6
22
IOCHRDY
O
I/O CHANNEL READY: Open drain output to the system bus which
when high indicates that the addressed I/O device is ready for the bus
transaction. The output is driven low when negated.
31
CLK
I
CLOCK: A free-running clock used to control internal timing
operations. A possible source is OSC, the 14.3 MHz ISA bus clock.
3
/IOCS16
O
I/O CHIP SELECT 16: Asserted (low) to indicate that the addressed
I/O window (/IOCSA, /IOCSB, /IOCSC or /IOCSD) supports 16-bit data
transfers. The user controls whether this signal is asserted or not
asserted for a specific chip select through values stored in the
EEPROM. See Table 12, EEPROM addresses 0x00D, 0x010, 0x013
and 0x016.
2
/MEMCS16
{DREQ7}
O
MEMORY CHIP SELECT 16{DREQ7}: In MEMORY mode, asserted
(low) to indicate that the addressed memory window supports 16-bit
data transfers. This signal will be asserted for a specific address
through values stored in the Plug and Play standard registers.
/MEMCS16 will be asserted for any assertion of /MCSA if bit 1 of
register 0x42 of logical device 0 is programmed to a ‘1’ by the Plug and
Play configuration software. It will also be asserted for any assertion
of /MCSB under the following conditions:
- In submodes 0 and 1, if bit 1 of register 0x4A of logical device 0 is
set to a ‘1’ by the Plug and Play configuration software.
- In submodes 2 and 3, if bit 1 of register 0x42 of logical device 1 is
set to a ‘1’ by the Plug and Play configuration software.
Note that the assertion of /MEMCS16 is based only on the comparison
of the LA<23:17> signal lines against the corresponding upper and
lower address values programmed for the two chip selects by the Plug
and Play configuration software. Thus, the output will be asserted for
the entire 128K address block(s) within which the chip select lies. The
entire block must be all 8 bits or all 16 bits. Problems may arise if only
a portion of the block is associated with the 16-bit resource and another
portion with an 8-bit resource. This output is open drain when negated.
In DMA mode, this pin is an an ouput indicating that the peripheral
device is ready to transfer data. Used for both read and write
operations. If not configured as an output the pin is maintained in the
three-state condition.
28
/REFRESH
{DRQB}
I
REFRESH CYCLE{ DMA REQUEST B}: In MEMORY mode this pin
is an active low input which indicates that a refresh cycle is in progress
on the platform. Memory chip select outputs are not generated while
this input is asserted. In DMA mode, it is an active high input which is
asserted to indicate that the device is requesting bus ownership to
transfer data.
ISA Bus Interface Signals (continued)
PIN
NUMBER
SYMBOL
TYPE
DESCRIPTION
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| MB86832-80PFV-G | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86831 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86831-80PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86831PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-100PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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