參數(shù)資料
型號(hào): MB86602C
廠商: Fujitsu Limited
英文描述: SCSI-II Protocol Controller (Differential)(SCSI-II 協(xié)議控制器)
中文描述: 支持SCSI - II協(xié)議控制器(差異)(支持SCSI - II協(xié)議控制器)
文件頁(yè)數(shù): 42/57頁(yè)
文件大?。?/td> 487K
代理商: MB86602C
MB86602C
42
Hex. A4 A3 A2 A1 A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Output data register (first)
Output data register (second)
Direct control register
(Reserved)
SEL/RESEL-ID register
Command register
Data block register (MSB)
Data block register (LSB)
Data byte register (MSB)
Data byte register
Data byte register (LSB)
MC byte register
Diagnostic control register
Transfer mode register
Transfer period register
Transfer offset register
Window address register
DO7
DO15 DO14 DO13 DO12 DO11 DO10 DO9
DC7
0
0
0
0
0
0
0
SI7
0
0
0
CM7
CM6
CM5
CM4
BL15 BL14 BL13 BL12 BL11 BL10
BL7
BL6
BL5
BL4
BY23 BY22 BY21 BY20 BY19 BY18 BY17 BY16
BY15 BY14 BY13 BY12 BY11 BY10
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DO8
0
0
SI0
CM0
BL8
BL0
0
0
0
0
0
0
0
SI2
CM2
SI1
CM1
BL9
BL1
CM3
BL3
BL2
BY9
BY8
0A
0
1
0
1
0
BY7
BY6
BY5
BY4
BY3
BY2
BY1
BY0
0B
0C
0D
0E
0F
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
DG7
TM7
0
0
WA7
DG6
0
0
0
WA6
DG5
0
0
0
0
0
0
DG3
0
TP3
TO3
WA3
DG2
0
TP2
TO2
WA2
DG1
0
TP1
TO1
WA1
DG0
0
TP0
TO0
WA0
TP4
TO4
0
Bit allocation
Address
Register
I
LIST OF REGISTERS
1. BASIC Control Registers (for write)
Hex. A4 A3 A2 A1 A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0 Input data register (first)
1 Input data register (second)
0 SPC status register
1 Nexus status register
0 Interrupt status register
1 Command step register
0 Data block register (MSB)
1 Data block register (LSB)
0 Data byte register (MSB)
1 Data byte register
Data byte register (LSB)
0
MC byte register
1 SCSI control signal status register
0 Transfer mode register
1 Transfer period register
0 Transfer offset register
1 Modified byte register
DI7
DI15
SS7
NS7
IS7
CS7
BL15 BL14 BL13 BL12 BL11 BL10
BL7
BL6
BL5
BY23 BY22 BY21 BY20 BY19 BY18 BY17 BY16
BY15 BY14 BY13 BY12 BY11 BY10
DI6
DI14
SS6
NS6
IS6
CS6
DI5
DI13
SS5
NS5
IS5
CS5
DI4
DI12
×
×
IS4
CS4
DI3
DI11
×
×
IS3
CS3
DI2
DI10
SS2
NS2
IS2
CS2
DI1
DI9
SS1
NS1
IS1
CS1
BL9
BL1
DI0
DI8
SS0
NS0
IS0
CS0
BL8
BL0
BL4
BL3
BL2
BY9
BY8
0A
0
1
0
1
BY7
BY6
BY5
BY4
BY3
BY2
BY1
BY0
0B
0C
0D
0E
0F
Note:
×
indicates data is undefined. (0 or 1).
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
SC7
TM7
×
×
×
SC6
×
×
×
×
SC5
×
×
×
MB5
SC4
×
TP4
TO4
MB4
SC3
×
TP3
TO3
MB3
SC2
×
TP2
TO2
MB2
SC1
×
TP1
TO1
MB1
SC0
×
TP0
TO0
MB0
Bit allocation
Address
Register
2. BASIC Control Registers (for read)
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