- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98009 > MB86290APFVS (FUJITSU LTD) GRAPHICS PROCESSOR, PQFP240 PDF資料下載
參數(shù)資料
| 型號： | MB86290APFVS |
| 廠商： | FUJITSU LTD |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, PQFP240 |
| 封裝： | 0.50 MM PITCH, PLASTIC, QFP-240 |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 380K |
| 代理商： | MB86290APFVS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁
MB86290A
8
Graphics Memory Interface Pins
Notes :
The graphics memory interface connects the MB86290A to the external memory used for graphical image
data. The interface can directly accept 64 Mbit SDRAM (with a 16-bit or 32-bit data bus) without
any external circuit.
The data signal can be selected between 64 bits and 32 bits. To use the 32-bit signal, leave the MD32 to
MD63 and MDQM4 to MDQM7 pins open.
Connect the MCLKI pin to the MCLKO pin.
Clock Input Pins
Notes :
The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal
operating clock and display dot clock. Usually input 4 Fsc (
= 14.31818 MHz) . The internal PLL generates
the internal operating clock signal of 100.22726 MHz and the display reference clock signal of 200.45452
MHz.
The internal operating clock signal to be used can be selected between the clock signal (CLK input
multiplied by 7) generated by the internal PLL and the bus clock BCLKI input to the host CPU interface.
Select the BCLKI input to use the host CPU bus at 100 MHz.
Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to
the S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for
300
s or more.
Pin Name
Input/output
Function
MD0 to MD63
Input/output
Graphics memory bus data
MA0 to MA13
Output
Graphics memory bus data
CKE
Output
Clock enable
MRAS
Output
Row address strobe
MCAS
Output
Column address strobe
MWE
Output
Write enable
MDQM0 to MDQM7
Output
Data mask
MCLKO
Output
Graphics memory clock output
MCLKI
Input
Graphics memory clock input
Pin Name
Input/output
Function
CLK
Input
Clock input signal
S
Input
PLL reset signal
CKM
Input
Clock mode signal
CKM
Clock Mode
L
Select internal PLL output.
H
Select host CPU bus clock (BCLKI) .
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86295S-PB-GS | GRAPHICS PROCESSOR, PBGA256 |
| MB86603 | SCSI BUS CONTROLLER, PQFP176 |
| MB86604A-PF | SCSI BUS CONTROLLER, PQFP100 |
| MB86605PMT | SCSI BUS CONTROLLER, PQFP144 |
| MB86606PMT | SCSI BUS CONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86290APVSR-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86291A | 制造商:Fujitsu 功能描述: |
| MB86291APFVS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Graphics Display Controller |
| MB86291APFVS-G-BND-DLE1 | 制造商:FUJITSU 功能描述:CONTROLLER GRAPHDISPLAY QFP208 |
| MB86291APFVSGBNDL | 制造商:Fujitsu 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。