參數(shù)資料
型號(hào)： MB86290APFVS
廠商： FUJITSU LTD
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, PQFP240
封裝： 0.50 MM PITCH, PLASTIC, QFP-240
文件頁(yè)數(shù)： 24/26頁(yè)
文件大?。?/td> 380K
代理商： MB86290APFVS
MB86290A
7
Video Interface Pins
* : Input voltage level : 5 V tolerant
Notes :
The video interface contains an 8-bit D/A converter to output analog RGB signals.
Using an additional external circuit, the video interface can use CSYNC signals to generate composite
video signals.
The video interface can output analog RGB signals synchronized with external video signals. The mode
for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with
a set dot clock as for normal display.
The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon
reset.
Terminate the AOUTR, AOUTG, and AOUTB pins with a resistance of 75 .
Input 1.1 V to the VREF pin. Between this pin and analog ground, insert a bypass capacitor (one with
a superior high-frequency characteristic such as a laminated ceramic capacitor) .
Connect the ACOMPR, ACOMPG, and ACOMPB pins to the 0.1F ceramic capacitor ahead of the analog
power supply.
Connect the VRO pin to the analog ground with a 2.7 k resistor.
The input voltage levels of the HSYNC, VSYNC, and EO signals are 5 V tolerant. Do not input 5 V to
these pins with the power supply off. (See s ABSOLUTE MAXIMUM RATINGS.)
For noninterlaced display in external synchronization mode, input “0” to the EO pin, for example, using
a pull-down resistor.
The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low
level signal to select video.
Pin Name
Input/output
Function
DCLKO
Output
Display dot clock signal output
DCLKI
Input
External synchronous dot clock signal input
AOUTR
Analog output
Analog video (R) signal output
AOUTG
Analog output
Analog video (G) signal output
AOUTB
Analog output
Analog video (B) signal output
HSYNC
Input/output*
Horizontal sync signal output
Horizontal sync signal input in external synchronization mode
VSYNC
Input/output*
Vertical sync signal output
Vertical sync signal input in external synchronization mode
CSYNC
Output
Composite sync signal output
EO
Input/output*
Even/odd-number field identification output
Even/odd-number field identification input in external synchronization mode
GV
Output
Graphics/video select signal
VREF
Analog output
Reference voltage input pin
ACOMPR
Analog output
R-signal compensation pin
ACOMPG
Analog output
G-signal compensation pin
ACOMPB
Analog output
B-signal compensation pin
VRO
Analog output
Reference current setting pin
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