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參數(shù)資料
| 型號： | MB86290APFVS |
| 廠商： | FUJITSU LTD |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, PQFP240 |
| 封裝： | 0.50 MM PITCH, PLASTIC, QFP-240 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 380K |
| 代理商： | MB86290APFVS |
MB86290A
5
Host Interface Pins
Note : The host interface can connect the MB86290A to the SH4 (SH7750) or SH3 (SH7709) manufactured by
Hitachi Ltd. or to the V832 manufactured by NEC without any external circuit in between. (Using the
SRAM interface allows the MB86290A to use another CPU.) The host CPU is set by the MODE pins as
shown below.
Notes :
The host interface transfers data signals at a fixed width of 32 bits.
There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address
space.
The external bus can be used at an operating frequency of 100 MHz Max.
The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level
sets the wait state in the SH3 mode. Note that the XRDY signal is a tristate output.
The host interface supports DMA transfer using an external DMA controller.
Pin Name
Input/output
Function
MODE0,
MODE1
Input
Host CPU mode select
RESET
Input
Hardware reset
D0 to D31
Input/Output
Host CPU bus data
A2 to A24
Input
Host CPU bus address (Connect A24 to MWR in V832 mode.)
BCLKI
Input
Host CPU bus clock
BS
Input
Bus cycle start signal
CS
Input
Chip select signal
RD
Input
Read strobe signal
WE0
Input
D0 to D7 write strobe signal
WE1
Input
D8 to D15 write strobe signal
WE2
Input
D16 to D23 write strobe signal
WE3
Input
D24 to D31 write strobe signal
RDY
Output
Tristate
Wait request signal (“0” for wait state with SH3; “1” for wait state with SH4 or
V832)
DREQ
Output
DMA request signal (active low with both SH and V832)
DRACK/
DMAAK
Input
InputDMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DTACK/TC
Input
DMA transfer strobe signal (Connect this to TC in V832 mode. SH
= active high,
V832
= active low)
INT
Output
Host CPU interrupt signal (SH
= active low, V832 = active high)
TEST0 to
TEST5
Input
Test signal
MODE1 pin
MODE0 pin
CPU Type
LL
SH3
LH
SH4
HL
V832
HH
Reserved
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86290APVSR-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86291A | 制造商:Fujitsu 功能描述: |
| MB86291APFVS | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Graphics Display Controller |
| MB86291APFVS-G-BND-DLE1 | 制造商:FUJITSU 功能描述:CONTROLLER GRAPHDISPLAY QFP208 |
| MB86291APFVSGBNDL | 制造商:Fujitsu 功能描述: |
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