參數(shù)資料
型號: MB814400C-70
廠商: Fujitsu Limited
英文描述: CMOS 1 M ×4 BIT Fast Page Mode DRAM(CMOS 1 M ×4 位快速頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 1米× 4位快速頁面模式的DRAM的CMOS(1米× 4位快速頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 12/27頁
文件大小: 327K
代理商: MB814400C-70
12
MB814400C-60/MB814400C-70
Fig. 6 – EARLY WRITE CYCLE (OE=“H” or “L”)
t
ASC
t
RAH
t
ASR
t
WCS
t
CAH
t
DS
“H” or “L”
ROW
ADD
VALID
DATA IN
COLUMN
ADD
HIGH-Z
DESCRIPTION
A write cycle is similar to a read cycle except WE is set to a Low state and OE is a “H” or “L” signal. A write cycle can be implemented
in either of three ways - early write, OE write (delayed write), or read-modify-write. During all write cycles, timing parameters t
RWL
,
t
CWL
and t
RAL
must be satisfied. In the early write cycle shown above t
WCS
satisfied, data on the DQ pin is latched with the falling
edge of CAS and written into memory.
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
CAS
WE
DQ
(Output)
A
0
to A
9
DQ
(Input)
V
IH
V
IL
t
RC
t
RAS
t
CSH
t
RSH
t
CAS
t
RCD
t
CRP
t
RAD
t
CAL
t
RAL
t
WCH
t
DH
t
RP
相關(guān)PDF資料
PDF描述
MB814400D-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動態(tài)RAM)
MB814400D-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁面存取模式動態(tài)RAM)
MB814405C-60 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
MB814405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
MB814405D-60 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM)
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參數(shù)描述
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