參數(shù)資料
型號(hào)： MB814400D-60
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 1位快速頁(yè)面模式的DRAM（的CMOS 4米× 1位速頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 1/24頁(yè)
文件大小： 274K
代理商： MB814400D-60
1
DS05-10164-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 1 M
FAST PAGE MODE DYNAMIC RAM
×
4 BIT
MB814400D-60/-70
CMOS 1,048,576
×
4 bit Fast Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB814400D is a fully decoded CMOS Dynamic RAM (DRAM) that contains 4,194,304 memory cells
accessible in 4-bit increments. The MB814400D features a “fast page” mode of operation whereby high-speed
random access of up to 1,024-bits of data within the same row can be selected. The MB814400D DRAM is ideally
suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications
where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby
current of the MB814400D is very small, the device can be used as a non-volatile memory in equipment that
uses batteries for primary and/or auxiliary power.
The MB814400D is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon process.
This process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft
errors and extends the time interval between memory refreshes. Clock timing requirements for the MB814400D
are not critical and all inputs are TTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB814400D-60
MB814400D-70
RAS Access Time
60 ns max.
70 ns max.
CAS Access Time
15 ns max.
20 ns max.
Address Access Time
30 ns max.
35 ns max.
Randam Cycle Time
110 ns min.
125 ns min.
Fast Page Mode Cycle Time
40 ns min.
45 ns min.
Low power Dissipation
Operating current
605 mW max.
550 mW max.
Standby current
11 mW max. (TTL level)/5.5 mW max. (CMOS level)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1,048,576 words
×
4 Bit organization
Silicon gate, CMOS, 3D-Stacked capacitor
Cell
All input and output areTTL compatible
1024 refresh cycles every16.4 ms
Early write or OE controlled write capability
RAS only CAS-before-RAS, or Hidden
Refresh
Fast page Mode, Read-Modify-Write
capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料
PDF描述
MB814400D-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1位速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405C-60 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405C-70 CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB814405D-60L 1M ×4BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
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