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參數(shù)資料
| 型號： | MB8117805A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 200萬× 8位超頁模式動態(tài)RAM的CMOS（200萬× 8位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 26/30頁 |
| 文件大?。?/td> | 569K |
| 代理商： | MB8117805A-70 |
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MB8117805A-60/MB8117805A-70
CAS
Fig. 19 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
Parameter
Unit
Min.
Max.
ns
No.
Min.
Max.
—
—
55
50
(At recommended operating conditions unless otherwise noted.)
MB8117805A-60
Symbol
35
—
—
ns
35
71
72
73
77
—
—
ns
70
99
—
—
ns
90
99
—
—
ns
90
MB8117805A-70
Access Time from CAS
Column Address Hold Time
CAS to WE Delay Time
CAS Pulse width
RAS Hold Time
Note: Assumes that CAS-before-RAS refresh counter test cycle only.
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
10
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
70
69
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
“H” or “L”
Valid Data
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held
Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
10
are defined by the on-chip refresh counter.
Column Addresses: Bits A
0
through A
9
are defined by latching levels on A
0
-A
9
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 2,048 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 2,048 times with addresses generated by the
internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 2,048 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
t
CSR
t
RP
t
CP
t
RCS
t
FCAH
t
ASC
t
CWL
t
WP
t
CHR
t
FRSH
t
RWL
t
FCWD
t
DH
t
DS
t
DZC
t
OED
t
DZO
t
OEZ
t
OEH
VALID DATA IN
COLUMN ADDRESSES
t
FCAC
t
FCAS
HIGH-Z
HIGH-Z
t
OEA
HIGH-Z
t
ON
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