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參數(shù)資料
| 型號： | MB8117805A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2M ×8 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 200萬× 8位超頁模式動態(tài)RAM的CMOS（200萬× 8位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 24/30頁 |
| 文件大小： | 569K |
| 代理商： | MB8117805A-70 |
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MB8117805A-60/MB8117805A-70
CAS
CAS
Fig. 16 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
Fig. 17 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
A
0
to A
10
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
RAS
DQ
(Output)
“H” or “L”
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row
addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is
latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
“H” or “L”
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held
Low for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh address
counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented
in preparation for the next CAS-before-RAS refresh operation.
DQ
(Output)
t
RC
t
RP
t
ASR
t
RPC
t
RAH
t
CRP
t
OH
t
CRP
t
RAS
t
OFF
ROW ADDRESS
HIGH-Z
t
RC
t
RAS
t
RPC
t
CPN
t
CSR
t
CHR
t
RP
t
OFF
t
OH
t
CSR
t
CPN
HIGH-Z
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