參數(shù)資料
型號(hào)： MB8117405B-60
廠商： Fujitsu Limited
英文描述： 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM)
中文描述： 4米× 4位快速頁面模式動(dòng)態(tài)RAM（的CMOS 4米× 4位快速頁面存取模式的RAM）
文件頁數(shù)： 28/31頁
文件大?。?/td> 588K
代理商： MB8117405B-60
28
MB8117405B-50/-60
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
Valid Data
—
—
—
—
MB8117405B-60
Min
.
—
MB8117405B-50
Min.
—
Unit
Parameter
Max.
50
ns
No
.
Max.
45
—
—
—
—
69
70
71
72
73
Symbol
(At recommended operating conditions unless otherwise noted.)
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
35
70
50
50
ns
35
63
45
45
Column Address Hold Time
ns
ns
ns
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
HIGH-Z
HIGH-Z
t
OEH
HIGH-Z
VALID DATA IN
COLUMN ADDRESSES
CAS
Fig. 20 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
V
IH
V
IL
V
IH
V
IL
RAS
A
0
to A
10
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
WE
DQ
(Input)
OE
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function-
ality of CAS-before-RAS refresh circuitry. If, after a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS
is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
10
are defined by the on-chip refresh counter.
Column Address: Bits A
0
through A
10
are defined by latching levels on A
0
-A
10
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 2048 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-
RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses generated
by the internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
DQ
(Output)
t
FRSH
t
RP
t
CHR
t
CSR
t
CP
t
FCAS
t
FCAH
t
ASC
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
DZC
t
OED
t
FCAC
t
OEZ
t
ON
t
DZO
t
FCWD
t
OEA
t
WHR
t
WSR
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