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參數(shù)資料
| 型號(hào)： | MB8117405B-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM) |
| 中文描述： | 4米× 4位快速頁面模式動(dòng)態(tài)RAM（的CMOS 4米× 4位快速頁面存取模式的RAM） |
| 文件頁數(shù)： | 27/31頁 |
| 文件大?。?/td> | 588K |
| 代理商： | MB8117405B-60 |
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MB8117405B-50/-60
Fig. 19 – TEST MODE SET CYCLE (A
0
to A
10
, OE = “H” or “L”)
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
D
OUT
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
RAS
t
RP
t
CPN
t
CSR
t
CHR
t
WSR
t
WHR
t
OFF
t
OH
HIGH-Z
DESCRIPTION
Test Mode ;
The purpose of this test mode is to reduce device test time to one sixteenth of that required to test the device conventionally.
The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of sixteenth bits which are selected by the address combination of
CA0 and CA1. In the write mode, data is written into sixteenth cells simultaneously. But the data must be input from DQ1 only. In the
read mode, the data of sixteenth cells at the selected addresses are read out from DQ and checked in the following manner.
When the sixteenth bits are all “L” or all “H”, a “H” level is output.
When the sixteenth bits show a combination of “L” and “H”, a “L” level is output.
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 10ns from the specified value in the data sheet.
t
RC
, t
RWC
, t
RAC
, t
CAC
, t
AA
, t
RAS
, t
RSH
, t
CAS
, t
CSH
, t
RAL
, t
CAL
, t
RWD
, t
CWD
, t
AWD
, t
CPWD
, t
RHCP
.
CAS
WE
RAS
t
RC
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