參數(shù)資料
型號： MB8117400A-50
廠商： Fujitsu Limited
英文描述： CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 4米× 4位快速頁面模式的DRAM（的CMOS 4米× 4位快速頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 5/27頁
文件大?。?/td> 304K
代理商： MB8117400A-50
5
MB8117400A-50/MB8117400A-60/MB8117400A-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. Since
only eleven address bits (A
0
to A
10
) are available, the row and column inputs are separately strobed by RAS and
CAS as shown in Figure 1. First, eleven row address bits are input on pins A
address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS).
Both row and column addresses must be stable on or before the falling edges of RAS and CAS, respectively. The
address latches are of the flow-through type; thus, address information appearing after t
RAH
(min.)+ t
T
is automatically
treated as the column address.
0
-through-A
10
and latched with the row
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways–an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
-DQ
4
) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fan out of two TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions:
t
RAC
:
t
CAC
:
t
AA
:
t
OEA
:
from the falling edge of RAS when t
RCD
(max.) is satisfied.
from the falling edge of CAS when t
RCD
is greater than t
RCD
(max.).
from column address input when t
RAD
is greater than t
RAD
(max.).
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the
output buffers remain in a high-impedance state during the entire cycle.
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp
Supply Voltage
V
CC
4.5
5.0
5.5
V
0
°
C to +70
°
C
V
SS
0
0
0
Input High Voltage, all inputs
V
IH
2.4
—
6.5
V
Input Low Voltage, all inputs/outputs*
V
IL
–0.3
—
0.8
V
1
1
1
相關PDF資料
PDF描述
MB8117400A-60 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM)
MB8117400A-70 CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM)
MB8117400B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM)
MB8117400B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM)
MB8117405A-60 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM)
相關代理商/技術參數(shù)
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MB8117800A-60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB8117800A-70 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
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