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參數資料
| 型號： | MB8117400A-50 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 4米× 4位快速頁面模式的DRAM（的CMOS 4米× 4位快速頁面存取模式動態(tài)內存） |
| 文件頁數： | 23/27頁 |
| 文件大?。?/td> | 304K |
| 代理商： | MB8117400A-50 |
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MB8117400A-50/MB8117400A-60/MB8117400A-70
DESCRIPTION
Test Mode ;
The purpose of this test mode is to reduce device test time to one sixteenth of that required to test the device conventionally.
The test mode function is entered by performing a WE and CAS-before-RAS (WCBR) refresh for the entry cycle.
In the test mode, read and write operations are executed in units of sixteenth bits which are selected by the address combination of
CA
0
and CA
1
. In the write mode, data is written into sixteenth cells simultaneously. But the data must be input from DQ
1
only. In the read
mode, the data of sixteenth cells at the selected addresses are read out from DQ and checked in the following manner.
When the sixteenth bits are all “L” or all “H”, an “H” level is output.
When the sixteenth bits show a combination of “L” and “H”, an “L” level is output.
The test mode function is exited by performing a RAS-only refresh or a CAS-before-RAS refresh for the exit cycle.
In test mode operation, the following parameters are delayed approximately 10 ns from the specified value in the data sheet.
t
RC
, t
RWC
, t
RAC
, t
CAC
, t
AA
, t
RAS
, t
RSH
, t
CAS
, t
CSH
, t
RAL
, t
CAL
, t
RWD
, t
CWD
, t
AWD
HIGH-Z
“H” or “L”
DQ
Fig.15 - TEST MODE SET CYCLE (A
0
to A
10
, OE = “H” or “L”)
RAS
WE
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
t
RAS
t
RP
t
RC
t
CHR
t
CSR
t
CPN
t
WHR
t
WSR
t
OH
t
OFF
V
OH
V
OL
相關PDF資料 |
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| MB8117400A-60 | CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM) |
| MB8117400A-70 | CMOS 4 M ×4 BIT Fast Page Mode DRAM(CMOS 4 M ×4位快速頁面存取模式動態(tài)RAM) |
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| MB8117405A-60 | CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級頁面存取模式動態(tài)RAM) |
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